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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
FEBRUARY 2004 REV. 1.0.1
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz Centralized Clock interface for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75 or 120 applications. The XRT85L61 extracts either 2048kHz or 1544 kHz clock signals from an E1 (2.048 MHz), T1 (1.544 Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz clock signals from the 64kHz reference clock input. The XRT85L61 includes an on-chip crystal-less jitter attenuator with 32 bit FIFO that can either be enabled or disabled. FEATURES
* Supports 75 and 120 (E1), 100 (T1) applications.
* Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
* Receive loss of signal (RLOS) output * Meets Telcordia GR-1244-CORE Section 3.4.1 R327 specification
* Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
* Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
* Single +3.3V Supply Operation * Logic inputs accept either 3.3 V or 5 V levels * 28 pin TSSOP package
APPLICATIONS
* Extracts 2048 kHz, 1544 kHz clock and data components
* Universal Clock Synchronization for G.703 Telecom
Formats
* Extracts 64 KHz and 8 kHz, 400 Hz clock information
* Line Code Violation alarms * On-chip digital clock recovery circuit
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
RCLKINV DATA_INV DATAMUT JAEN Reference Inputs MCLK1
(1.544 MHz for T1)
* T1/E1 Line Receiver with Clock and Data Recovery * DSLAM
Master Clock Generator RPOS RNEG RCLK
(64kHz,1544kHz or 2048kHz) 8 kHz (for 64 kbps)
MCLK2
(2.048 MHz for E1 or 64 kbps)
RTIP Line Side
(T1 or E1 or 64 kbps input)
Clock Extractor Rx Equalizer Peak Detector and Slicer Clock and Data Recovery Jitter Attenuator Line code and clock violation Detector
RRING
400 Hz
(for 64 kbps)
S1 S2 S3
RCLK_LCV/AIS 8 kHz_LCV/BPV 400 Hz_LCV RLOS
Mode Select T1, E1 or 64 kbps
LOS Detector
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ORDERING INFORMATION
PART NUMBER XRT85L61IG PACKAGE 28 Lead TSSOP OPERATING TEMPERATURE RANGE -40C to +85C
FIGURE 2. PIN OUT OF THE XRT85L61
MCLK1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18
RCLKINV
MCLK1 JAEN MCLK2 JAVDD JAGND ICT RTIP RRING AVDD AGND S1 S2 S3 NC
1 2 3 4 5
MCLK2 JAEN JAVDD JAGND ICT RTIP RRING AVDD
28 27
DATA_LCV RCLK_LCV
RCLKINV DATA_INV
8 KHz_LCV 400 26 Hz_LCV RCLK_LCV/ AIS 8 KHz
25 Hz 8 KHz_LCV/ BPV 400
RLOS
24
AGND S1
DVDD DGND RCLK
400 Hz_LCV 8 KHz
6 7 8 9 10 11 12 13 14
23
S2 S3 NC
17 16 15
RPOS 400 Hz 22 RNEG
RLOS 21 DATMUT
20 19 18
DVDD DGND RCLK RPOS RNEG DATMUT
17 16 15
2
XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS................................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61 ............................................................................................................................... 1
ORDERING INFORMATION.....................................................................................................................2
FIGURE 2. PIN OUT OF THE XRT85L61............................................................................................................................................ 2
TABLE OF CONTENTS ............................................................................................................I PIN DESCRIPTIONS ..........................................................................................................3 ELECTRICAL CHARACTERISTICS ..................................................................................6
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 6 DC Electrical Characteristics ....................................................................................................................6
FUNCTIONAL DESCRIPTION ...........................................................................................7
1.0 OPERATING MODE: ..............................................................................................................................7
1.1 64 KHZ CLOCK MODE: .................................................................................................................................... 7
TABLE 1: OPERATING MODE SELECTION........................................................................................................................................... 7 TABLE 2: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT ............................................................................... 7 1.1.1 64 KHZ + 8 KHZ CLOCK EXTRACTION ...................................................................................................................... 8 1.1.2 64 KHZ + 8 KHZ + 400 HZ CLOCK EXTRACTION ...................................................................................................... 8 TABLE 3: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT ............................................................................ 8 FIGURE 3. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0) ................................................................................... 8
1.2 2048 KHZ RZ E1 MODE ................................................................................................................................... 9
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1) ................................................................... 9 FIGURE 5. E1 PULSE MASK (G.703) ................................................................................................................................................ 9 TABLE 4: G.703 SPECIFICATION E1................................................................................................................................................ 10
1.3 2048 KHZ NRZ MODE .................................................................................................................................... 11
FIGURE 6. E1 CLOCK SIGNAL WAVE SHAPE - G.703 ...................................................................................................................... 11 TABLE 5: G.703 2048 KHZ CLOCK INTERFACE ............................................................................................................................... 11
1.4 1544 KHZ T1 MODE ....................................................................................................................................... 12
FIGURE 7. G.703 DS1 WAVE FORM............................................................................................................................................... 12
2.0
AIS DETECTION TIMING ....................................................................................................................13
FIGURE 8. AIS DETECTION FOR E1 MODE ...................................................................................................................................... 13 FIGURE 9. AIS DETECTION FOR T1 MODE ...................................................................................................................................... 13
ORDERING INFORMATION...................................................................................................................14 REVISION HISTORY............................................................................................................................. 15
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN # 1 SYMBOL MCLK1 TYPE I DESCRIPTION Reference T1 Clock input: This signal is an independent 1544 kHz clock with accuracy better than + 32 ppm and duty cycle within 40% to 60%. This clock provides timing source for the PLL clock recovery circuit in T1 mode.
NOTE: If T1 mode is not used, this clock is not necessary for the device to operate.
2 JAEN I Jitter Attenuator Enable: Tie this pin "High" to enable the Jitter Attenuator. When enabled, a 32 bit FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 k resistor
3 MCLK2 I Reference E1 and 64 kHz Clock Input: This signal is an independent 2048 kHz clock with accuracy better than + 50 ppm and duty cycle within 40% to 60%. This clock provides timing source for the PLL clock recovery circuit in E1 and 64 kHz mode.
NOTE:
To reduce intrinsic jitter when the JA is enabled, it is recommended to have a reference clock with an accuracy of 25 ppm or better. If E1 mode or 64 kHz mode is not used, this clock is not necessary for the device to operate.
4 5 6
JAVDD JAGND ICT
*** *** I
VDD for Jitter Attenuator (3.3V 5%) Jitter Attenuator Ground In circuit Testing When this pin is grounded, all output pins are Tri-stated for testing purposes.
NOTE: Internally Pulled up with 50 k resistor
7 8 9 10 RTIP RRING AVDD AGND I I *** *** Receive Positive Input Receive Negative Input Analog VDD (3.3V 5%) Analog Ground
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN # 11 SYMBOL S1 TYPE I Mode Select DESCRIPTION
S1 0 0 0 0 1 1 1 1
S2 0 0 1 1 0 0 1 1
S3 0 1 0 1 0 1 0 1
MODE 64 kHz + 8 kHz 64kHz+8kHz+400Hz E1 RZ E1 NRZ T1 T1 (output full width data) E1
(output full width data)
Reserved
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG are 1 RCLK wide.
12 13 14 15 S2 S3 NC DATMUT I I *** I Mode Select Mode Select This pin must be grounded for normal operation Data Muting: Connect this pin "High" to mute data output to "Low" state at RPOS/ RNEG. The RLOS pin can be connected to this pin to mute the output when RLOS occurs.
NOTE: Internally Pulled down with 50 k resistor
16 RNEG O Receive Negative Data Output: The data is half clock cycle wide. Receive Positive Data Output: The data is half clock cycle wide Receive Clock Output Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock Digital Supply Ground Digital Supply Voltage (3.3V 5%) Receive Loss of Signal Output 400 Hz Clock output for 64 kHz Operation 8 kHz clock output for 64 kHz Operation Line Code Violation for 400 Hz This pin will stay "High" when 400 Hz is not in sync.
17
RPOS
O
18
RCLK
O
19 20 21 22 23 24
DGND DVDD RLOS 400Hz 8 kHz 400Hz_LCV
*** *** O O O O
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
PIN DESCRIPTIONS
PIN # 25 SYMBOL 8 kHz_LCV/ BPV TYPE O DESCRIPTION Line Code Violation for 8 kHz in 64 kHz operation Bipolar Violation: In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated at this pin. This pin will stay "High" when 8 kHz is not in sync. Receive Clock Violation. In 64 kbps operation, every missing pulse will cause this pin to go "High" for half the clock cycle AIS Indication In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay "High" for 250 s in E1 RZ mode, and in T1 mode, AIS will stay "High" for 3 ms. Data Invert: Connect this pin "High" to output active "Low" data at RPOS/RNEG.
26
RCLK_LCV/AIS
O
27
DATA_INV
I
NOTE: Internally Pulled down with 50 k resistor
28 RCLK_INV I Receive Clock Invert: Connect this pin "High" to align the data to change at the falling edge of RCLK.
NOTE: Internally Pulled down with 50 k resistor
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage Range ESD Theta-JA Theta-JC - 65C to + 150C - 40C to + 85C -0.5V to +6.0V 2000 V 68C/W 13C/W
ELECTRICAL CHARACTERISTICS (TA = 25C, VDD = 3.3 V + 5%, UNLESS OTHERWISE SPECIFIED)
SYMBOL PARAMETER MIN.
TYP.
MAX.
UNITS
DC Electrical Characteristics
VDDD VDDA VIL VIH VOL VOH IL CI CL DC Supply Voltage (Digital) DC Supply Voltage (Analog) Input Low Voltage Input High Voltage Output Low Voltage, IOUT = -4.0mA Output High Voltage, IOUT = 4.0mA Input Leakage Current* Input Capacitance Output Load Capacitance 5 25 2.0 0 2.4 3.135 3.135 3.3 3.3 3.465 3.465 0.8 VDD 0.4 VDD 10 V V V V V V A pF pF
NOTE: * Not applicable to pins with pull-down resistors.
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
FUNCTIONAL DESCRIPTION
The XRT85L61 is an integrated BITS (Building Integrated Timing Supply) Clock Generator. Simplified block diagram of the chip is shown in Figure 1. The XRT85L61 extracts the clock signals from the following synchronization lines:
s s s s s
Balanced 100 lines with 1544 kbps DS1 pattern. Balanced 120 or unbalanced 75 lines with 2048 kbps RZ pattern. Balanced 120 or unbalanced 75 line with 2048 kbps NRZ pattern. Balanced 110 line with 64 kbps having 8 kHz violations; a "64 kHz + 8 kHz sync pattern. Balanced 110 line with a 64 kbps pattern having both 8 kHz and 400 Hz violations; a "64 kHz + 8 kHz + 400 Hz" sync pattern.
1.0 OPERATING MODE: The operating mode for the XRT85L61 is shown in Table 1. TABLE 1: OPERATING MODE SELECTION
S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 MODE 64 kHz + 8 kHz 64 kHz + 8 kHz + 400 Hz E1RZ E1NRZ T1 T1 (full width) E1 (full width) Reserved DATA OUTPUT AT RPOS / RNEG RZ RZ RZ RZ RZ
1.1
64 kHz Clock Mode:
The XRT85L61 receives the 64 kbps ternary RZ signal. Two modes of 64 kHz operation is possible by selecting S1, S2 and S3 as shown in Table 1. TABLE 2: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT
FREQUENCY Signal Format (A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ (a) AMI with 8 kHz Bipolar Violation (b) AMI with 8 kHz Bipolar Violation removed at every 400 Hz. Alarm should not occur against the amplitude range from 0.63 V to 1.1 V
Alarm Condition
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE 3: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT
FREQUENCY Load Impedance Transmission Media Pulse Width (FWHM) Amplitude 110 resistive Symmetric Pair Cable < 7.8 0.78 s < 1 V 0.1 V (A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
1.1.1
64 kHz + 8 kHz Clock Extraction
The input data is shown in Figure 3. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation. Both the 64 kHz and 8 kHz components are extracted from the composite received signal and presented at the 64 kHz and 8 kHz output pins. FIGURE 3. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)
Missing Pulse
RTIP/ RRING
Missing Pulse or Wrong Polarity Pulse
V V V
64kHz Clock
Missing Pulse
RPOS
Not Valid Violation
RNEG
V
8kHz Clock
Missing Pulse
RClk_LCV
If Pulse Missing at RTIP/RRING
out of sync
8kH_LCV
Missing Pulse
Not Valid Violation
Missing Pulse or No Violation Bit
1.1.2
64 kHz + 8 kHz + 400 Hz Clock Extraction
Figure 4 shows the input data for this mode. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation removed every 400 Hz. The 64 kHz, 8 kHz and 400 Hz components are extracted from the composite received signal and presented at the RClk, 8 kHz and 400 Hz output pins.
NOTE: The inputs are not aligned with all output signals. The above diagram is used to depict the output activity when the input signals have errors.
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1)
V1 nV V2 V1
V2
nV
125 s (8 kHz) (8 kHz)
125s (8 kHz)
125 s (8 kHz)
125s (8 kHz)
(400 Hz) (400 Hz) L CV if nV is Missing
NOTES: 1. V1 and V2 indicate AMI code-rule violations, and give the 8kHz timing. 2. V1 and V2 have different violation polarity with respect to each other. 3. nV indicates no violation (violation stealing) and gives the 400 Hz timing.
1.2
2048 kHz RZ E1 Mode
In this mode, the XRT85L61 receives a standard E1 signal as shown in Figure 5. Table 4 gives the details of the E1 pulse. FIGURE 5. E1 PULSE MASK (G.703)
26 9 ns (2 4 4 + 2 5 )
20%
10%
V = 10 0%
10%
20%
19 4 ns (2 4 4 - 5 0 )
N o m in a l p u l s e
50%
244 ns
10%
488 ns (2 4 4 + 2 4 4 ) N o te - V c o rre sp o n d s t o t h e n o m in al p ea k v a lu e .
20%
9
10%
0%
10%
10%
21 9 ns (2 4 4 - 2 5 )
XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
TABLE 4: G.703 SPECIFICATION E1
PULSE Pulse Shape (nominally rectangular) Pair(s) in each direction Test Load Impedance Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal Pulse Width Ratio of the amplitudes of positive and negative pulses at the center of the pulse interval Ratio of the widths of positive and negative pulses at the nominal half amplitude Maximum peak to peak jitter at an output port INTERFACE All Marks of a valid signal must conform with the mask irrespective of the sign. The value V corresponds to the nominal peak value. One coaxial pair 75 Resistive 2.37 V 0 0.237 V 244 ns 0.95 to 1.05 0.95 to 1.05 Refer to ITU-T G.823 specification One symmetrical pair 120 Resistive 3V 0 0.3 V
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
1.3
2048 kHz NRZ Mode
In this mode, XRT85L61 receives 2048 kbps synchronization signal as shown in Figure 6. FIGURE 6. E1 CLOCK SIGNAL WAVE SHAPE - G.703
T 30 T 30 T 30 T 30 T 30 T 30 +V
+V1
0
- V1
T 4
T 4 T
T 4
T 4
-V
T 1 8 1 8 9 0 0 -9 2
S h a d e d a r e a in w h ic h s ig n a l s h o u ld b e m o n o to n ic
T A v e r a g e p e rio d o f s y n c h r o n iz in g s ig n a l
F IG U R E 2 1 /G .7 0 3 W a v e s h a p e a t a n o u tp u t p o rt
TABLE 5: G.703 2048 KHZ CLOCK INTERFACE
PULSE Frequency Pulse Shape INTERFACE 2048 kHz 50 ppm The signal must conform with the mask. The value V corresponds to maximum peak value The value V1 corresponds to minimum peak value Coaxial pair 75 Resistive 1.5 0.75 Symmetrical pair 120 Resistive 1.9 1.0
Pair(s) in each direction Test Load Impedance Maximum peak value (Vop) Minimum peak value (Vop) Maximum jitter at an output port
0.05 UI peak to peak measured within the frequency range f1 = 20 Hz to f4 = 100 kHz
NOTE: This value is valid for network timing distribution equipment. Other values may be specified for timing output ports of digital links carrying the network timing.
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
1.4
1544 kHz T1 Mode
In this mode, the XRT85L61 receives a standard DS1 signal as shown in Figure 7. FIGURE 7. G.703 DS1 WAVE FORM
N or m aliz ed a m p litu de 1 .5
1 .0
0 .5
0
- 0.5
- 1.0 - 1.0
- 0.5
0
0 .5
1 .0
1 .5
T 1 5 2 86 7 0 -9 8
T im e , in U n it In te rv als
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
2.0
AIS DETECTION TIMING
In E1 mode, AIS is set when the incoming signal has 2 or less Zeros in sequence of 512 bits. AIS will stay "High" for 250 s and AIS is cleared upon receiving three or more zeros in the subsequent 512 bits (250s) time-frame. Figure 8 shows the AIS timing. FIGURE 8. AIS DETECTION FOR E1 MODE
250s E1 250s
DATA
0
0
0
0
0
AIS
In T1 mode, AIS is cleared when 5 or more zeros is detected in the subsequent 4632 bits (3 ms) time-frame. Figure 9 shows the AIS timing for T1 mode. FIGURE 9. AIS DETECTION FOR T1 MODE
3 ms T1 3 ms
DATA
0
0
0
0
0
0
0
0
0
AIS
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XRT85L61 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
ORDERING INFORMATION
PART NUMBER XRT85L61IG PACKAGE 28 Lead TSSOP OPERATING TEMPERATURE RANGE -40C to +85C
PACKAGE OUTLINE DRAWING
D
28 15
E1 E
1 S eatin g P lane
14
C A2 A
e
B
A1
L
N ote: T he control dim ension is in th e m illim eter colum n
IN C H E S SYMBOL
A A1 A2 B C D E E1 e L
M ILLIM E TE R S M IN
0.85 0.05 0.80 0.19 0.09 9.60 6.30 4.30 0.45 0
M IN
0.033 0.002 0.031 0.007 0.004 0.378 0.248 0.169 0.018 0
MAX
0.047 0.006 0.041 0.012 0.008 0.386 0.260 0.177 0.030 8
MAX
1 .20 0 .15 1 .05 0 .30 0 .20 9 .80 6 .60 4 .50 0 .75 8
0.025 6 B S C
0.65 B S C
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XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
REV. 1.0.1
REVISION HISTORY
REVISION # P1.0.1 P1.0.2 P1.0.3 1.0.0 1.0.1 DATE August 2002 November 2002 December 2002 January 2004 February 2004 original Edits to text Ordering information changed from XRT85L61IV to XRT85L61IG Final Release Added description for MCLK1 and MCLK2. CHANGES
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet February 2004.
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